Today's science increasingly uses simulation to model and understand the world around us.
To enable them to be faster, more accurate and to model larger phenomena, scientists are using supercomputers, the field of expertise of High-Performance Computing. As demand for computing power grows, these machines need to be ever more powerful. However, the reduction in transistor size provided for by Moore's Law is no longer sufficient to drive the development of processors, the core of supercomputer power. So, to continue to meet this demand, these machines are becoming increasingly complex. And the performance of HPC applications depends on the inter-actions between the numerous application behaviours, the increasingly complex processor architectures and the choices made by the various software stacks. The effort required to optimise the performance of applications on machines is therefore ever greater. One way of simplifying these optimisation efforts and achieving better application performance is to bring together all the HPC players in a codesign environment for the design of future machines. In such an environment, where the choices made by designers are driven by the interests of the applications, the processors and software stack will be adapted to the needs of future users. This is even more important since the recent arrival of the Arm environment in HPC, representing 10% of the total computing power of the Top500 with just 6 machines. This offers manufacturers greater freedom in their choice of processor characteristics. However, in such a codesign environment, it is necessary to use a performance prediction approach that takes into account the impact of the choices made by all the players in order to carry out a viable exploration of the design space. In the course of this thesis, we set up a performance projection approach adapted to our definition of a re-codesign environment grouping the actors and aspects of application performance into 3 groups: the application, the software stack and the hardware. This model is presented in three stages to carry out the projection from an application/software stack/source hardware triplet, which is accessible, to a future target triplet of interest, which is inaccessible. These steps are: the characterisation of performance on our three aspects, followed by the analysis of performance on the source triplet, which will finally lead to a projection of performance towards the target triplet as a function of the differences between the parameters of the latter and the source triplet. This approach is then implemented using a representation based on the Roofline model, in which we focus on the maximum performance achievable by the triplets and project the per- formances with an assumption of conservation of architectural efficiency. We then use this model to analyse and explore hardware parameters such as the size of vectors or the choice of memory type on different archi- tectures of Arm cores.
Finally, we are extending this exploration to multicore architectures by refining the characterisation of the bandwidth and work done by each core. The use of this approach focuses on the exploration of application and software stack parameters on a future architecture of interest for HPC: the EPI (European Processor Initiative) processor.